Analysis and design of a low-voltage high-frequency LDMOS transistor

For a low voltage lateral double-diffused MOS (LDMOS) transistor, the output performance has been improved in terms of f/sub MAX/. This is done by decreasing the output capacitance and thus decreasing the total output conductance. Extraction of the model parameters has been made and the most efficient parameter to improve was identified and linked to a specific part of the transistor structure. Layout changes in the n-well/p-base region were done as the result of the model analyses and finally, the modified devices were processed. Measurements on the improved devices showed results that closely, matched the expected, and f/sub MAX/ was increased with 30% and only a slight decrease in f/sub T/. Finally, the capacitance reduction in the n-well/p-base junction was measured by direct. measurements.