Design of compact high-frequency output buffer for testing of analog CMOS VLSI circuits

A compact high-frequency CMOS analog buffer for testing purposes is presented. A prototype integrated in a 3- mu m CMOS process drives a 15-pF, 10-k Omega load and shows a bandwidth of 25 MHz, a large-signal setting time to 1% of less than 90 ns, and a dynamic range over 77 dB. Power consumption is 2.4 mA per cell. Its small size (less than 0.18 mm/sup 2/) makes it suitable for monitoring low-capacitance internal nodes of analog or mixed-mode VLSI circuits.<
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