Neural parallel-hierarchical-matching scheduler for input-buffered packet switches

Input-buffered packet switches boosted with high-performance schedulers achieve near-100% throughput. Several authors have proposed the use of neural schedulers. These schedulers have a fast theoretical convergence, but the standard deviation of the number of iterations required can be arbitrarily large. In a previous paper, the authors proposed a hybrid digital-neural scheduler, HBRTNS, with bounded response time: O(N) clock steps. As an evolution of that concept, the authors present a two-stage neural Parallel-Hierarchical-Matching scheduler (nPHM), which generates high quality solutions in few clock steps. We present numerical comparisons with diverse state-of-the-art algorithms and the ideal output-buffered case.