An FPGA-based video compressor for H.263 compatible bitstreams

This paper presents an architecture for video encoding according to the H.263 standard for video conference systems. The implementation is based on an commercial available FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, could already be implemented and is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time procession of several video streams in a single reconfigurable chip. Soon the progress of FPGA integration density will make it possible to implement coding options, too. The use of FPGA technology enables adapting the hardware to various protocols and environments by software and therefore to save development time and hardware costs.