A high-retention 2T embedded DRAM with cell-body toggle scheme

In this work, we present an embedded DRAM utilizing body-controlled 2T gain cell. The memory bit-cell consists of a high-V
_TH
NMOS write transistor and a standard-V
_TH
NMOS read transistor. Since the negative cell-body toggle signal couples up the data `1' storage voltage after data write, this body-controlled technique provides 72% enhanced retention time. In addition, since the subthreshold leakage through the write device is drastically reduced by the negative body bias, the proposed technique exhibits 14 times stronger write disturbance immunity. Simulation results from a 32-kbit eDRAM implemented in a 130 nm triple-well logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.