Comparison of flip chip technologies on rigid polyimide with respect to reliability and manufacturing costs

Flip chip interconnect technology has seen extensive growth with the demands for electronics miniaturization. Applying flip chip interconnection can potentially achieve smaller size, better performance, higher reliability and, with the development of new materials and processes, lower cost. In this study, the Space Department of the Johns Hopkins University Applied Physics Laboratory is working jointly with HyComp, and Fraunhofer Institute of Reliability and Microintegration, to investigate the feasibility and reliability of several types of interconnect technologies for flip chips. Attentions will be focused on the interconnections between integrate circuits (IC's) and the substrate as they are indicated as weak linkages for long-term reliability. Emerging interconnect technologies, such as applying anisotropic conductive adhesive (ACA), Au stud bumping, and Stud Bump Bonding (SBB), will be discussed in this paper. All assemblies will be subjected to series of reliability tests, including temperature cycling, thermal shock, vibration, 85/spl deg/C/85% RH temperature humidity, and radiation tests. In-situ resistance measurements will be made to continuously monitor performance of interconnects. The test results can be used to evaluate and assess the reliability of the interconnect technology for future space application. Furthermore, a cost comparison of all investigated technologies will be given in this study. Thus we evaluated not only the technological but also the economical potential of each technology.