An evolutionary approach for data path synthesis

This paper presents an evolutionary approach to solve the data path allocation problem in high-level synthesis. From a behavioral description and a set of constraints, the method generates a VHDL RTL data path and a controller structure with a minimal cost. The proposed method was implemented using the C language on a Linux workstation. We tested our method on various high-level synthesis benchmarks, all yielding good solutions in a short time. Designs were validated using Altera Max+Plus II.