Junctionless GAA nanowire transistor: Towards circuit application

In this paper we have presented a Junctionless GAA nanowire in the 20nm technology node. Junctionless are an alternative to inversion mode transistors. Nowadays device dimensions are miniaturized to achieve better functionalities and high packing density. However, the fabrication challenges are escalating in each advancement of technology nodes due to the precision ion implantation and optimized lithography process steps in such Nano-scale ranges. This work demonstrates both n-type and p-type Junctionless nanowire transistors, which predict impressive performances with high immunity towards short channel effects (SCEs). Further, the devices are integrated to investigate the CMOS circuit application and the results show a desired functionality with respect to ideal Sub-threshold slope(SS), low leakage current (I
_off
), high on-off current ratio (I
_on
/I
_off
), and a noise margin about 40% of the supply voltage.