Area, power and temperature optimization during binary decision diagram based circuit synthesis

To fulfill the demands of increased functionality, large numbers of logic blocks are rooted within very large scale integration (VLSI) circuit at sub-nanometer technology. This results into increased power-densities within the chip and power-density directly converges into temperature. The increase in temperature reduces the yield of the circuit. On the contrary, reduction of power and power-density increases the area. So, there is a trade-off among area, power, and power-density. Binary Decision Diagram (BDD) based combinational circuit synthesis is quite popular. Suitable input variable ordering through BDDs can optimize the said circuit parameters. Proposed work presents a Genetic Algorithm (GA) based approach to select a suitable BDD ordering in its reduced ordered form to optimize the objective parameters without performance degradation. Proposed approach saves more than 44% in area and power, and 6% in power-density with respect to auto-order and in-order BDD representation. An improvement of 14.07% in area and 6.99% in power is observed with respect to earlier literature approach.