Low-noise CMOS differential-amplifier design using automated-design methodology

The increasing complexity of Integrated Circuits (ICs) and requirement of accurate design, made the automated design technique a necessity. The design of analog circuit involves satisfying different sets of constraints along with determination of optimal design parameters value that result in optimized performance of the circuit. Presence of noise in a circuit affect its performance, hence proper analysis become a necessity in realization a high performance circuit (low-noise circuit). This paper presents a new automated design methodology of designing a low-noise Differential-amplifier with current mirror load, with both MOS transistor length and width optimization, considering various performance specifications as constraints. Nature-inspired heuristic optimization algorithm has an ability to give acceptable approximate solution within a reasonable time. Here, Human-Behavior Based Particle Swarm Optimization (HPSO) algorithm is used as an intended candidate to determine optimal design parameters value to realize a low-noise amplifier with minimum total circuit area. The MATLAB and CADENCE tool is linked to verify the purposed automated design methodology using UMC 0.18 μm parameters technology. Further, the performance of the purposed automated design methodology is compared with previous design methodology to check its efficiency in terms of speed, time and robustness.