Probabilistic error detection and correction in switched capacitor circuits using checksum codes

In the past, techniques for error detection in linear digital and analog circuits using checksum codes have been developed and shown to be highly efficient. While error detection is a solved problem, error correction has proved to be difficult due to the time and area overheads involved in diagnosing failed system states and correcting them in real-time. To solve the correction problem, real-time probabilistic correction mechanisms have been proposed for digital circuits that correct for state errors in a probabilistic manner, circumventing the process of accurate error diagnosis. Such a technique is difficult to apply to continuous-time analog circuits without altering the analog transfer function, due to the nature of error feedback mechanisms involved. However, switched-capacitor circuits offer intrinsic advantages; they replicate analog continuous-time behavior while retaining the benefits of a digital clock. In this work, we show how errors in switched-capacitor circuits can be detected and corrected, using probabilistic correction algorithms, by taking advantage of the separation in time afforded by the use of a digital clock between error-free and error-affected clock cycles of the circuit. By probabilistically correcting errors in real-time before the onset of future clock cycles, the advantages offered by digital clocks are exploited to deliver high-fidelity analog performance in switched-capacitor filters resulting in significant SNR benefits at low cost.