Design with sub-10 nm FinFET technologies

• The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended — This is classical "Design Technology Co-optimization" (DTCO) • Only increasing over time • Memory transistor design must anticipate the required — Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells — Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood — The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact