Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC

In this paper, a low power 4-bit 400 MS/s standard cell based flash Analog-to-Digital Converter (ADC) is presented. The proposed flash ADC uses comparators based on the logic gates. Relationship between the input voltage and comparator reference voltage defines the output of comparator to be '1' or '0'. The comparator is followed by the gain booster and encoder. Low power consumption is achieved by effectively switching the comparators from active mode to standby mode. This switching activity is defined by the control signal. The proposed ADC is implemented at the transistor level in 180 nm CMOS, N-well technology with 1.8 V supply voltage and was simulated using Cadence Spectre simulator. Simulation results show the power reduction upto 66% when compared to conventional architecture. The measured spurious-free dynamic range (SFDR) is 30.202 dB and Effective Number of Bits (ENOB) is 3.71 bits with a 1.71 MHz input at a sampling rate of 400 MS/s. The proposed ADC consumes about 3.9 mW of power with figures of merit (FOM) of 0.745 pJ/conversion-step.