Efficient FPGA Implementation of the SHA-3 Hash Function

In this paper, three different approaches are considered for FPGA based implementations of the SHA-3 hash functions. While the performance of proposed unfolded and pipelined structures just match the state of the art, the dependencies of the structures which are folded slice-wise allow to further improve the efficiency of the existing state of the art. By solving the intra-round dependencies caused by the θ step-mapping with the pre-computation of values and by improving the memory mapping, it is possible to reduce the required area resources and obtain shorter datapath. This allows to achieve an efficiency improvement of at least 50% in regard to the state of art. This work also provides an overview of the achievable performance and cost for different folding/unrolling options.