Optimizing the flux and torque estimator of DTC in FPGA by using low-area square root calculator

This paper presents an alternative to improve the implementation of the torque and flux estimator for the Direct Torque Control (DTC) of induction motor drives in Field Programmable Gate Array (FPGA). The square root architecture is optimized to have low hardware resources utilization, by reducing the number of logic elements used, and subsequently contributing to reducing the power consumption. This is achieved by sharing the common hardware and eliminating parallel computation in the square root calculator, which is implemented by using the non-restoring algorithm. The proposed strategy was successfully implemented in ALTERA Cyclone II FPGA and the functionality of the system was validated via functional simulations.