An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

This paper presents a row-based design methodology covering cell placement, clock tree synthesis, and routing steps for large SFQ circuits. The proposed placement tool initiates by running a state-of-the-art CMOS placer, which places fixed-height but variable-width cells in rows on the chip. Cells in each row are then grouped together such that each group contains at most k cells with the same logic level. Next, for clock routing, this paper proposes HL-tree, which adopts an H-tree with passive transmission line connections to distribute the clock to groups, and within each group, a linear path composed of splitters and Josephson transmission lines (JTLs) provides the clock to cells. Increasing k reduces the chip area, but also may incur a performance loss. To evaluate the effectiveness of the proposed approach, place-and-route results of a 32-bit Kogge-Stone adder for different values of k are reported. By using this new design methodology, the overall chip area can be reduced by 27% compared with the results of a conventional CMOS placement accompanied by an H-tree clock network.