VLSI architecture for color mosaic image/video sequences

A Novel VLSI Architecture has been developed for Color Mosaic Images. The architecture was designed for implementation on an FPGA. The proposed work presents the integration of Color Image Mosaicing and Encoder Architecture in order to mosaic image/video sequences in real time. Novel algorithms for the image mosaicing have been designed using ASM charts. The image mosaicing architecture is coded using Verilog meeting the requirements to RTL Coding rule. Using this algorithm, a new architecture with a high degree of pipelining and parallelism suitable for FPGA/ASIC implementation has been designed. It has been completely verified using a complete Test bench for color pictures of sizes of up to 1600 × 1200 pixels.