15 GHz 25 dBm multigate-cell stacked CMOS power amplifier with 32 % PAE and ≥ 30 dB gain for 5G applications

A three-stage stacked FET CMOS power amplifier (PA) for the 12.7 to 15.3 GHz frequency range is presented. The PA achieves more than 30 dB linear gain with saturated output power of 25.1 dBm (320 mW) and peak power added efficiency (PAE) of 32.4 % at 13.5 GHz. The PA is implemented in 45 nm CMOS SOI technology. High gain is achieved with two cascode pre-driver stages and a final high power stage. The output stage comprises 512 four-stack multigate-cell devices to allow high voltage swings and correspondingly high output power. The effective gate width of the output device is 614 μm. To the authors knowledge, combination of power and efficiency achieved in this work are the highest reported for CMOS PAs in the 15 GHz band. The amplifier occupies an area of 1 × 1 mm
²
including pads.