Numerical analysis of thermal effects in SOI MOSFET Flip-Chip packages: Multi-scale studies on isolated transistors and global simulations

We present numerical simulations of thermal phenomena in SOI MOSFETs flip-chip packages. We consider the effects of package environment on isolated transistors performing multi-scale Finite Elements thermal simulations. Furthermore, we perform a complete thermal analysis of a microchip in a flip-chip package. We build a robust Finite Elements model of a typical ten-level Back End of Line (BEoL) in order to evaluate the effects that metal interconnects of the BEoL have on local and global temperature elevation. In order to perform a multi-scale simulation, we compute equivalent thermal properties for composite components that we apply to the macroscopic model for obtaining coherent results. Homogenized values show that the conductivity of the BEoL is one order of magnitude higher in the lateral direction than in the vertical one, with values ranging between 50 - 100 W/mK laterally and between 1 - 5 W/mK in the vertical direction. Therefore, the spreading of heat takes place mainly laterally through metal lines. Results in the microscopic model confirm that heat flowing towards the heat sink passes mainly through metal interconnects. The hot spot temperature elevation is around 90 K for a transistor with gate length L of 30 nm and active width W of 0.5 μm, value that is lower than for the hot spot at wafer level in the same transistor. We analyze the impact of the density of metal interconnects on temperature elevation, deducing relative variations of up to 100% on the temperature of the first metal level. Macroscopic inspection of a typical 28 nm CMOS Flip-Chip product shows that copper pillars create a path for heat transfer, resulting in hot spots on the top of the Ball Grid Array (BGA) and cold areas at active level. The temperature difference at chip level is around 12 K, with values depending on the distribution of copper pillars and the thickness of the Silicon bulk. We analyze the impact of a variation in the pitch between copper pillars on the maximum temperature, verifying that a higher pitch causes a variation of up to 8 K on maximum temperature in extreme cases. We propose an accurate compact model that predicts the impact of copper pillars placement based on approximation of equivalent thermal properties. Finally, we deduce that, independently of the molding compound presence, increasing the Silicon bulk thickness causes a homogenization in the temperature map at chip level, as the temperature difference is around 12 K for a bulk of 110 μm decreasing to 4 K for a bulk of 770 μm.