Circuit Techniques For A Wide Word I/O Path 64 Meg DRAM

The high rate data transfer between CPU and memory infuture high performance systems requires the 64 Meg DRAM and generations beyond to take a new design approach. Fast RAS access time together with a wider I/O path are key DRAM performances indices for achieving high bandwidth CPU-MEMORY data operations. In this paper a novel Hierarchical Multi-Datalines (HMD) Architecture with a wide I/O path and high speed circuit design techniques used to implement this architecture in a 64 Meg Dram are descibed.