Increase power density and simplify designs with 3D SiP modules

This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules. It will provide more details on SiP eco-system, co-design, construction, materials and circuit topology. Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more real estate toward end-user applications - all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example, in wearable products, the semiconductor industry has recently seen an increase in the use of system-in-package (SiP) technology for users who want simpler, more flexible designs and need to fulfill challenging space requirements. And we expect to see this trend continue.