Theoretical and experimental analysis of capacitance and mobility in InGaAs

InGaAs devices are candidates to replace Si devices in future technology nodes due to their promising transport properties. Recently, CMOS-compatiple replacement metal gate (RMG) InGaAs-on-insulator (InGaAs-OI) FinFETs with record performance have been reported [1]. Further optimization and identification of limiting factors by TCAD simulation requires calibration and validation of the underlying device models to measurements of fundamental quantities in devices which are fabricated under similar process conditions as applied in the target technology. Key quantities are trap profiles leading to Fermi-level pinning as well as bulk and long-channel effective mobility. While such investigations have already been done for sample devices [2, 3], we report in this work corresponding measurements for RMG InGaAs-OI technology, calibrate and validate device simulation to these measurements and compare the results with previous literature.