10 Gb/s radiation-hard VCSEL array driver

We present an R&D program to develop an ASIC that contains a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver operating at 10 Gb/s per channel, yielding an aggregated bandwidth of 120 Gb/s. The design of the 10 Gb/s array driver ASIC is based on a prototype ASIC for driving a VCSEL array at 5 Gb/s. We will briefly describe the design of the 5 Gb/s ASIC that was fabricated in a 130 nm CMOS process. Two ASICs were irradiated with 800 MeV protons to a dose of 0.92×10
¹⁵
1-MeV n
_eq
/cm
²
and remain operational. For the 10 Gb/s VCSEL array driver ASIC, we have submitted for fabrication a four-channel test chip using a 65 nm CMOS process. The circuit design together with the result from a simulation of the extracted layout with parasitic capacitance and inductance will be presented.