265-GHz, 10-dB gain amplifier in 65-nm CMOS using on-wafer TRL calibration

In this paper, a 65-nm CMOS amplifier MMIC operating around 265 GHz is presented. To obtain a small signal gain of the amplifier in a frequency region close to F
_max
(Maximum oscillation frequency) of a transistor, a neutralization technique of a feedback capacitance as well as a transistor model to neutralize it precisely are needed. For this purpose, the key is a de-embedding technique. To extract the intrinsic transistor characteristics from a test pattern for measurement, we employ an on-wafer TRL (Through-Reflect-Line) calibration method. In this method, the calibration patterns including Through, Reflect, and Line are fabricated on the same wafer with the transistor for modeling. With the help of the precise model based on on-wafer TRL, we can successfully obtain a gain of 10dB around 265 GHz, and an excellent agreement with simulation and measurement results.