OIV-CMOS: A novel approach towards leakage power reduction

In this paper we propose a new approach Overdriving Input Voltage CMOS (OIV-CMOS) to suppress static power. We found that in comparison to the base inverter, leakage power dissipation is appreciably reduced by 99.66% in OIV-CMOS at 180nm CMOS technology. It is also observed that for 2:1 MUX, the standby mode power consumption is reduced by 65.8% without effecting the performance and area of the circuit.