Power, signal integrity for 25-Gbps, 40-dB compensation signal conditioner for backplane architecture

A 25-Gbps/lane 40-dB compensation signal conditioner was developed. The target architecture was a long channel backplane with two connectors that have large reflections due to impedance discontinuities. Jitters originating from the power integrity (PI) and signal integrity (SI) are critical for a bit error rate (BER) less than 1E-12 because 1 unit interval (UI) is small at high speed. A technique for frequency dependent decap was designed to reduce the PI jitter. Also, a non-linear equalization for the reflections technique was designed to reduce the SI jitter. Our test chip can achieve 2.5 ps PI and 10.0 ps SI jitter, respectively. The sum of the PI and SI jitter can be reduced to less than 0.32 UI. Finally, our test chip can achieve a BER of less than 1E-12 for a 40-dB backplane with two connector traces.