High voltage RESURF DMOS process development using DFM techniques: a case study

Using design for manufacturability (DFM) techniques, it is possible to reduce the number of split runs of silicon, and the number of cycles of learning, needed in the development of a technology. This ultimately results in a process which consistently meets its specifications, and can be manufactured without great engineering effort. The purpose of this work was to develop a process which consistently yielded >400 V breakdown for applications in the power supply market. Based on the results of the analysis, a process was chosen which was proven after one iteration of silicon, thereby saving on development time and costs. This paper reviews the work undertaken to determine the optimum process flow in order to achieve the desired electrical performance, and analysis of the predicted breakdown distribution. A comparison is made to actual distributions obtained from silicon. Then, from experimental split lots, a sensitivity analysis is performed. A comparison of simulated and actual results are compared. In conclusion, we describe learning as a result of the analyses, and the advantages and disadvantages of the method/software and methodology used when running and gathering Si data.