A comprehensive platform for thermal studies in TSV-based 3D integrated circuits

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.