Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel

The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I
_on
/I
_off
current ratio (>10
⁷
) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P
⁺
channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.