Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.