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Electrical modeling and analysis of sidewall roughness of through silicon vias in 3D integration | IEEE Conference Publication | IEEE Xplore

Electrical modeling and analysis of sidewall roughness of through silicon vias in 3D integration


Abstract:

Electrical modeling of through silicon via (TSV) is very important for three dimensional (3D) system design and analysis. In this paper, we present our study on the impac...Show More

Abstract:

Electrical modeling of through silicon via (TSV) is very important for three dimensional (3D) system design and analysis. In this paper, we present our study on the impact of sidewall roughness on the TSV electrical performance in the ultra-broad band range. Our analysis shows that the root mean square height of the rough sidewall is comparable to the skin depth in extremely high frequency (> 20G HZ). Therefore, the effect of TSV sidewall roughness becomes one of the critical factors to be considered when modeling TSV in extremely high frequency band. An electrical model of TSV is proposed considering the effect of TSV sidewall roughness, as well as capturing the high frequency skin effect. The proposed circuit model is analytically calculated and validated with EM field simulations up to 50 GHz.
Date of Conference: 04-08 August 2014
Date Added to IEEE Xplore: 20 November 2014
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Conference Location: Raleigh, NC, USA

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