PDN Impedance Modeling for Multiple Through Vias Array in Doped Silicon

The power distribution network (PDN) impedance of 3-D-through silicon vias (TSVs) interposer layer is modeled by considering the metal-oxide-semiconductor (MOS) structure effects. The Lambert W function is proposed to simulate the change of depletion width with the bias voltage in the static field, and the high-frequency MOS capacitance is obtained while considering the charges at the semiconductor–insulator interface. Furthermore, based on the depletion width and the insulating dielectric layer assumption, the electrical model of power-ground TSVs pair is presented by combining the MOS capacitance with TSVs parasitic RLGC (resistance-inductance-capacitance-conductance). Finally, the PDN impedance characteristics of the 3-D-IC integrated system with multiple TSVs are performed by using the proposed multitransmission line and model reduction methods, and the importance of the capacitance is presented.