Performance estimation and architecture exploration of a video IP design in a smart phone SoC context

H.264 and HEVC are popular video standards for current and next generation systems. Texas Instruments has developed an IP architecture for real-time encode and decode of 4k×2k video streams at 30 frames per second (fps) or 1080p streams at 120 fps, on these standards. We present the architecture modeling methodology driving the design and performance validation of the IP. The IP model contains three key components. First, a pipeline modeling framework to capture the dynamic control flow across the algorithm blocks which are implemented as hardware modules. The framework enables quick representation of all pipeline configurations being considered. Second, micro-architecture models for the DMA engines. Third, trace players to generate the L2 and L3 traffic for various use-cases expressed as traces. The IP model is integrated into an SoC model to study the impact of system traffic on the L3 responses. We run simulations to evaluate the design w.r.t. the performance targets and for architecture exploration. Our H.264 results show that the IP meets targets for typical use-cases, but there is a risk for worst-case streams. Our HEVC architecture exploration study enables us to select recommended design configurations. We see this as a powerful methodology for performance validation and architecture definition.