Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO/sub 2/ interface quality and free from gate depletion. The gate sheet resistance is about 2 ohm//spl square/, nearly constant down to 0.05 /spl mu/m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 /spl Aring/ pure oxide has inferior charge-to-breakdown (Q/sub bd/) distribution under substrate (+V/sub G/) injection. However, a remote-plasma nitrided oxide (RPNO) can greatly improve the +V/sub G/ Q/sub bd/ distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L/sub gate//spl ap/0.07 /spl mu/m. For nMOS under +V/sub G/ direct tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J/sub p/) than n/sup +/ poly-gate device (by about an order magnitude larger). This higher J/sub p/ is believed due to the tunneling of valence-band electron and thus has no impact on the thin (t/sub ox//spl les/33 /spl Aring/) gate oxide reliability.