QSim: Framework for Cycle-accurate Simulation on Out-of-Order Processors based on QEMU

Researching the cycle level behavior of a processor running an application is crucial to understanding the modern computer architecture. To this end, detailed cycle level simulators are typically employed. In this paper, we present a co-simulation framework for out-of-order processors, called QEMU-based sim-outorder, or QSim for short. It's a combination of QEMU and sim-outorder, in which QEMU does functional simulation, and the simulation result is required by sim-outorder for clock-accurate simulation. In addition with the fast emulation speed of QEMU, the TB caching mechanism is introduced to further improve clockaccurate simulation by storing the previous simulation result in sim-outorder. We have implemented the original simoutorder simulation model and QSim for the C-SKY V2 architecture, which is a dedicated architecture for the embedded system. Experiments give a comparison of the two implementations and through the statistics of the instruction execution cycle it shows that (1) without TB cache, QSim can accelerate the clock-accurate out-of-order simulation by 11.44 times than the traditional simulator sim-outorder, which has the accuracy rate at 4.17% loss in average, meanwhile (2) with TB cache, QSim runs 71.91 times faster than sim-outorder, which has the average deviation rate at 20.33%.