A clock phase adjustment circuit for synchronizing multiple high-speed DEMUXs

A 2:16 DEMUX IC with clock phase adjustment has been successfully designed, fabricated, and tested as an interfacing component in 30 Gbps and higher transmission systems using HRL's 0.25 μm low power InP DHBT technology with f
_t
of 400 GHz. The novel clock phase adjustment circuit described here allows multiple DEMUXs to be automatically synchronized eliminating the need of complex clock recovery circuits. The IC uses 1460 DHBTs and consumes only 1.85 W of power demonstrating the feasibility of InP DHBTs in low power and large integration ICs.