Session 2: FPGAs and synthesis — Part I

One of the trends in ESL based design space exploration with fast turn-around is prototyping on FPGAs for faster simulation of various configurations of the model. The papers in this session leverage some of the synthesis and optimization techniques targeted for FPGA cores to facilitate just that. The first paper describes a Just-In-Time (JIT) compiler for FPGA soft processors. It explores a number of optimizations that target the FPGA architecture allowing significant speedups over the current state of the art. The second paper describes a two step optimization technique where in the first step, compile-time computable values are collected which are then used in a second step to apply optimizations to the CDFG representation of the input program.