Variation-aware deep nanometer gate performance modeling: An analytical approach

A complete set of analytical gate performance models is developed based on driving current analysis. Closed-form equations for gate delay and output slew are obtained, which capture the dependence on key process and design parameters, such as the input slew, threshold voltage, etc. Using these formulas, gate performance of various topologies is accurately predicted under both nominal and variational conditions. This work can be easily implemented to enhance fast statistical timing analysis, circuit optimization and aging characterization.