Incorporating interconnect, register, and clock distribution delays into the retiming process

A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delays. These delay components are incorporated into the retiming process by assigning register electrical characteristics (RECs) to each edge in the graph representation of a synchronous circuit. A matrix, called the sequential adjacency matrix (SAM), is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in existing retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and to continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. A branch and bound method is offered for the general retiming problem where the REC values are arbitrary. Certain monotonicity constraints can be placed on the REC values to permit the use of standard linear programming methods, thereby requiring significantly less computational time. These conditions and the feasibility of their application to practical circuits are presented. The algorithm is demonstrated on modified benchmark circuits and both increased clock frequencies and the elimination of all race conditions are observed.