A high performance BiCMOS process featuring 40 GHz/21 ps

A high performance BiCMOS process is presented which features 40 GHz cutoff frequency, 21 ps gate delay and 20 GHz divider circuits for the bipolar part together with 0.6 mu m CMOS. Deep trench isolation is used for low collector to substrate capacitances and high packing density. Concepts to decouple the bipolar from the CMOS building blocks for an uncompromised optimization of both device types are proposed and discussed.<
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