Front-end electronics for the readout of CdZnTe sensors

The CERN/spl I.bar/DxCTA is a front-end ASIC optimized for the readout of CdZnTe sensors. The chip is implemented in 0.25 /spl mu/m CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and CdZnTe pixel detectors.