An improved model for the charging characteristics of a dual-dielectric (MNOS) nonvolatile memory device

A computer-based model of the shift in the flat-band voltage by an applied gate bias pulse of a dual-dielectric gate MNOS device is presented. The model is used to predict the write characteristics of an MNOS device where the thickness of the SiO
2
layer ranges between 20-30 Å and that of the nitride layer between 300-600 Å. The results of the model are found to be in excellent agreement with experimental data. The shift in flat-band voltage versus applied symmetric gate bias pulses is presented with the thickness of the SiO
2
layer and the duration of the pulse as parameters. The shift in the flat-band voltage of an MNOS transistor is related to the electric charge trapped at the SiO
2
- Si
3
N
4
interface. This charge results from a discontinuity in the electric current in the SiO
2
and the Si
3
N
4
layers. The current through the SiO
2
layer is based upon the expression derived by Murphy and Good and differs in its pre-exponential [9] term from the previously used modified Fowler-Nordheim tunnel current expressions. The electric current in the Si
3
N
4
layer is considered to be primarily due to the Frenkel-Poole effect. However, for completeness, an ohmic current component for low electric fields and field emission current component for high electric fields are also included.