A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR

A cross-coupled two-path /spl Sigma//spl Delta/ architecture generates transmission zeros at 1/3 of the clock frequency, thereby achieving a mirror image free response. The chip uses 0.18 /spl mu/m CMOS technology and is clocked at 2/spl times/60 MHz with a 40 MHz IF. The modulator achieves an 86 dB SFDR with a 2.5 MHz bandwidth and consumes 150 mW from a 1.8 V supply.