Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST)

This paper reports on a novel Super Junction LDMOST in SOS technology (SJ-LDMOST) targeting Power Integrated Circuits (PICs) and discusses a CMOS compatible process used in the implementation of the device. The proposed structure uses a simple and practical method to achieve charge compensation between the n and p SJ-pillars and a uniform electric field distribution in the forward blocking mode. 3D device simulations indicate that a significant reduction of the specific on-resistance for a given breakdown voltage can be achieved over conventional RESURF devices using a realistic aspect ratio for the SJ pillars.