A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits

This paper proposes a novel finite-gain compensation technique that can be applied to low-voltage high-speed reset- and switched-opamp circuits. The proposed technique utilizes an auxiliary differential-difference amplifier (A-DDA) that senses and corrects the finite-gain error from the virtual ground of the main opamp (with the effective gain in the order of /spl beta/A/sup 2/) thus allowing the use of high-speed single-stage low-gain opamps (instead of usual low-speed two-stage amplifier with large power consumption) to achieve high-speed operation. Simulations of a reset-opamp 10-bit 100 MHz pipelined ADC in 1.2-V supply voltage are presented using 0.18 /spl mu/m CMOS, with the signal-to-noise-and-distortion ratio (SNDR) improved from 46.77 dB to 58.51 dB and thus verifying the effectiveness of the proposed circuit.