Elastic-buffer flow control for on-chip networks
Michelogiannakis, G.; Balfour, J.; Dally, W.J.
High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
Volume , Issue , 14-18 Feb. 2009 Page(s):151 - 162
Digital Object Identifier 10.1109/HPCA.2009.4798250
Summary:This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtual-channel buffers (VCBs). With this approach, the channels themselves act as distributed FIFO buffers. Without VCBs, and hence virtual channels (VCs), deadlock prevention is achieved by duplicating physical channels. We develop a channel occupancy detector to apply universal globally adaptive load-balancing (UGAL) routing to load balance traffic in networks using EBs. Using EBs results in up to 8% (12% for low-swing channels) improvement in peak throughput per unit power compared to a VC flow-control network. These gains allow for a wider network datapath to be used to offset the removal of VCBs and increase throughput for a fixed power budget. EB networks have identical zero-load latency to VC networks operating under the same frequency. The microarchitecture of an EB router is considerably simpler than a VC router because allocators and credits are not required. For 5 times 5 mesh routers, this results in an 18% improvement in the cycle time.
View citation and abstract |
Cart
