Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz
Nikaeen, P.; Murmann, B.
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Volume , Issue , 21-24 Sept. 2008 Page(s):161 - 164
Digital Object Identifier   10.1109/CICC.2008.4672048
Summary:A digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution ADCs is presented. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant nonidealities. Applying the method to a 14-bit, 155-MS/s ADC provides > 83 dB SFDR up to f_in = 470 MHz. The post-processing block is estimated to consume 52 mW and occupy 0.54 mm² in 90-nm CMOS.

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