A micro-programmable realtime image processor
Mori, T.; Aono, K.; Sakai, H.; Hasegawa, K.; Yamada, H.; Takemoto, T.
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Volume XXIX, Issue , Feb 1986 Page(s): 144 - 145
Digital Object Identifier  
Summary: A micro-programmable realtime image processor with an instruction cycle of 20ns will be described. A 7×7mm², 45K transistor chip has been designed in a self-aligned bipolar technology. Dissipation is 2.5W.

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