Modern FPGA constrained placement
Wai-Kei Mak
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Volume 2, Issue , 18-21 Jan. 2005 Page(s): 779 - 784 Vol. 2
Digital Object Identifier 10.1109/ASPDAC.2005.1466458
Summary:We consider the placement of FPGA designs with multiple I/O standards on modern FPGAs that support multiple I/O standards. We propose an efficient approach to solve the constrained I/O placement problem by 0-1 integer linear programming within a high performance placement flow. We derive an elegant 0-1 integer linear program formulation which is applicable not only for devices with symmetric I/O banks but also for devices with asymmetric I/O banks (i.e., different banks may have different sizes and/or support different subsets of I/O standards). Moreover, it is capable of handling user's prelocked I/Os. We also show that additional restrictions such as conditional usage of Vref pins can be easily incorporated. Our formulation involves only a small number of 0-1 integer variables independent of the device size or the number of I/O objects, hence our approach can comfortably handle very large problem instances. Extensive experimentation showed that the 0-1 integer linear program corresponding to a feasible instance of the constrained I/O placement problem can be solved in seconds.
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