Experiences with Soft-Core Processor Design
Plavec, F.; Fort, B.; Vranesic, Z.G.; Brown, S.D.
Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
Volume , Issue , 04-08 April 2005 Page(s): 167b - 167b
Digital Object Identifier   10.1109/IPDPS.2005.209
Summary: Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.

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